Intel Patents XBM: The New Memory Aims to Surpass HBM4 While Reducing Costs and Complexity

Intel has published a new patent describing a technology called XBM (Cross-Batch Memory), designed as a possible alternative to future HBM4 memories and aimed at increasing bandwidth while simultaneously reducing production and packaging costs. Alongside the ZAM project developed in collaboration with SAIMEMORY, Intel seems to be pursuing a completely independent path as well.

The patent, published on July 2, 2026, but filed on December 26, 2024, and identified by the leaker Underfox, describes a vertically stacked memory that maintains a footprint comparable to that expected for HBM4, but introduces substantial changes both in the structure of DRAM and in the communication interface.

The most innovative element concerns the realization of memory cells. In traditional DRAM, transistors are manufactured in the front-end-of-line (FEOL), which refers to the silicon layer of the chip. XBM proposes moving them to the back-end-of-line (BEOL), utilizing thin-film transistors integrated in the upper metal layers. This solution would increase efficiency in die area usage, allowing more space for vertical connections (Through-Silicon Via or TSV) while simultaneously increasing overall density and bandwidth.

This week, an Intel patent application was published, revealing its proposed Cross-Batch Memory (XBM), an ultra high-bandwidth memory that offers some significant improvements over the current standard, which could be a direct competitor to HBM4 in the near future.

Each die uses a configuration of 1T1C (one transistor and one capacitor) and contains about 1.5 GB of memory organized in 768 blocks arranged in a 32x24 matrix. The blocks are divided into eight channels, each made up of eight subchannels, while the stack can consist of eight or sixteen levels of memory.

The interface also represents a significant break from conventional HBM. HBM memories achieve their high bandwidth through an extremely wide parallel interface, on the order of 1024 bits per stack, which requires the use of an expensive silicon interposer. XBM replaces this approach with serial UCIe (Universal Chiplet Interconnect Express) connections operating up to 32 GT/s. The base die handles the serialization and deserialization of data, directing traffic to the processor or accelerator. According to Intel, this choice would eliminate the interposer, reducing package size and costs, making the memory more suitable for chiplet-based systems.

The patent devotes significant attention to reliability aspects as well. The base die integrates Built-In Self Test (BIST) functions, diagnostic and repair logic, redundant channels, and Built-In Self Repair (BISR) mechanisms designed to recover any defects that may arise after the assembly of the memory stacks. There are also reserve channels available to replace defective portions of memory, aiming to improve production yield.

Intel also describes different packaging configurations, including a Memory-on-Package (MoP) solution and a structure defined as "reversed overhang," designed to reduce the overall thickness of the package by eliminating some mechanical components that are normally necessary to limit substrate warping and directly powering the DRAM from the voltage regulator.

The company claims that XBM could match or exceed HBM4 in terms of density and bandwidth due to the greater number of TSVs and the new organization of the subchannels. Some analyses speculate potential performance increases possibly in the order of double compared to current generations, but the patent does not report official values for overall bandwidth or definitive specifications on capabilities.

As is always the case with a patent, there are no guarantees that the technology will reach the market. XBM does not appear in the company's public roadmaps, and several questions remain about the production feasibility of BEOL transistor-based DRAM, in addition to the limitations imposed by the current maximum speed expected by the UCIe standard of 32 GT/s. If the project were to continue, potential commercialization would likely be aimed for a period after 2030.