The relationship between Intel and the AVX-512 instruction set has been quite inconsistent in recent years regarding consumer CPUs. However, the upcoming Nova Lake generation seems poised to mark a stable return of the technology, at least according to the latest Linux kernel patches.

The last appearance of AVX-512 on an Intel client CPU was with the Tiger Lake generation, the 11th generation Core. Since then, the manufacturer has not offered support for this instruction set on chips targeted at the consumer market. Meanwhile, AMD has continued on a different path, integrating AVX-512 into both Zen 4 and Zen 5 processors, in both client and server environments, gaining ground in this aspect as well.

Last year, there were indications of a possible return of AVX-512 in future Intel CPU families, conveyed through AVX 10.2. Some patches hinted at extended support for both the Core and Xeon lines.

Nothing important here, just good to see #Intel client CPUs back in the #AVX512 arena:

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The latest updates to the Linux kernel now make this issue more concrete: support for AVX-512 is substantially confirmed for the Nova Lake lineup and for the upcoming client CPU families. Among the technical references identified is the implementation of the xor_gen() function based on AVX-512, enabled on architectures such as AMD Zen 4, Intel Sapphire Rapids, Rocket Lake, and, indeed, Nova Lake, all equipped with the AVX512F set.

The possible return of this technology is not a marginal detail. AVX-512 introduces 512-bit vector operations, which is double the width compared to standard AVX, with measurable benefits in certain workloads. For instance, on a Ryzen 9 9950X based on Zen 5 architecture, switching from AVX to AVX-512 produces improvements ranging from 26% to 43% depending on the number of sources involved in the calculation.

To understand the significance of this return, it is helpful to revisit the reason for its abandonment. The main cause lies in the hybrid architecture adopted by Intel since Alder Lake, which combines P-cores and E-cores within the same die. Only P-cores were able to handle AVX-512 instructions, while E-cores lacked this capability, leading to a situation of internal incompatibility within the chip. It should also be noted that Alder Lake, in its early stages, did indeed offer support for AVX-512, functionality that was later disabled in subsequent updates at the request of Intel itself to motherboard partners.

Nova Lake will also maintain a hybrid architecture, featuring Coyote Cove P-cores and Arctic Wolf E-cores. However, the architecture of the E-cores is much more modern and complete compared to that of previous chips, so we should see greater uniformity of characteristics between the two core types. It remains to be seen, with the actual arrival of Nova Lake, to what extent this reintroduction will help strengthen Intel's position in direct competition with rivals.