AMD Advancing AI 2026: AMD Hardware for Future AI Processing, Among GPUs, CPUs, and Robots

At CES 2026

During CES 2026, AMD unveiled, for the first time, some technical features of its CDNA 5 architecture and the Instinct MI400 accelerator family, designed for all AI-related processing needs in data centers. At the top of this range was the Instinct MI455X model, the GPU that was set to become the backbone of the AMD Helios rack platform, the weapon with which the American company intends to compete with NVIDIA for leadership in the training and inference of large language models.

Recently, during the Advancing AI 2026 event in San Francisco, AMD announced not only the Helios platform but also the Instinct MI455X solutions and sixth-generation EPYC processors, along with the next-generation AMD Pensando networking solutions. What was previewed at CES in January 2026 is now taking shape at Advancing AI, although we won’t see these products in the hands of partner companies for a few months.

Advancing AI is the annual event that AMD organizes to update customers, partners, and press on the expected hardware innovations in the data center space. CPUs, GPUs, systems, and infrastructure all oriented toward the world of artificial intelligence.

During the presentations and keynote by Lisa Su, it was clearly highlighted how artificial intelligence is increasingly at the center of data center processing. At the same time, AMD aims to offer its specialized solutions that can be adopted together for different processing areas, providing everything as a complete platform and approaching the market with the typical open philosophy that characterizes AMD's operations in both the consumer and enterprise sectors.

AMD Helios: The Rack for AI

AMD Helios well represents this approach: it is a rack developed on open standards, which integrates servers that house sixth-generation EPYC CPUs, CDNA 5 architecture-based MI455X GPUs, and AMD Pensando solutions to manage all the different types of interconnection.

A single Helios rack, developed in a double width according to the OCP Open Rack Wide standard, integrates 18 compute trays, each housing four Instinct MI455X GPUs paired with a single sixth-generation AMD EPYC processor from the Venice family, capable of offering up to 256 cores in Zen 6c-based versions.

In total, each Helios rack can accommodate up to 72 GPUs and 18 CPUs, aggregating to about 18,000 GPU processing units and over 4,600 CPU cores.

From a system perspective, a complete Helios rack can provide up to 2.9 exaFLOPS of FP4 computing and 1.4 exaFLOPS in FP8, with a total aggregated memory of 31 TB of HBM4 and an overall memory bandwidth around 1.4 PB/s. This data positions the AMD Helios solution in direct competition with NVIDIA's NVL72 rack, both in terms of computing power and memory capacity.

One of the most interesting elements of AMD Helios concerns the interconnection system of the different components that make up this platform. AMD has chosen not to use a proprietary fabric, instead opting for UALink (Ultra Accelerator Link), the open standard supported by Intel, Google, Microsoft, and Meta, conveyed over a physical Ethernet connection according to the approach called UALink-over-Ethernet (UALoE).

In the reference implementation developed together with HPE, switching is entrusted to Broadcom Tomahawk 6 switches, with an intra-rack scale-up bandwidth around 260 TB/s. For scale-out connectivity, that is, between different racks, the AMD Pensando Vulcano network card is used, capable of 800 Gbps per GPU according to the Ultra Ethernet Consortium standard.

AMD Instinct MI455X, the New AI GPU

At the heart of the AMD Helios platform is the Instinct MI455X GPU, built with 2-nanometer production technology combining HBM4 memory in a maximum quantity of 432 Gbytes, compared to the 288 Gbytes of the outgoing Instinct MI355X model. The Instinct MI455X GPU is a package that integrates twelve distinct chiplets, a number that signifies how AMD has systematically embraced chiplet design and the use of the best production technology for the type of component that needs to be integrated. The configuration includes two Graphics Compute Dies (GCD) produced on the TSMC N2 node at 2 nanometers, paired with two Memory Controller Dies (MCD) instead produced on the more mature N3P at 3 nanometers, all connected to sixteen stacks of HBM4 memory.

This is the first application for Instinct family solutions utilizing a 2-nanometer production process for compute dies, a choice that allows AMD to maximize logical transistor density precisely where it is needed, in the compute units, reserving the more economical 3-nanometer node with more established production yields for memory controllers and Infinity Fabric logic that do not require the same density.

The overall result is a package with 320 billion transistors, a 70% increase over the Instinct MI355X solution with CDNA 4 architecture, achieved also thanks to the use of more sophisticated production technologies. Compared to the Instinct MI355X, the bandwidth has significantly increased to 23.3 TB/s, almost tripling the previous figures. Memory has been increased by 50% compared to that of the Instinct MI355X, but more than anything, the processing power has noticeably grown: we are talking about 20 PetaFLOPS with MXFP8 processing and 40 PetaFLOPS with MXFP4 processing at peak, a value that is four times higher than what is achievable with the Instinct MI4355X.

AMD's Future Roadmap

For the first time, AMD has previewed its roadmap for upcoming Instinct solutions for the coming years, which will see new proposals launched annually. For 2027, the MI500 solutions are expected to introduce next-generation HBM memory and copper and optical interconnections. No specific information has been provided for the MI600 proposal, which is scheduled to debut in 2028 and is currently indicated as under development.

Venice: The Sixth Generation of EPYC CPUs

Shifting to the CPU aspect, AMD has presented the sixth generation of EPYC processors, codenamed “Venice.” Following a path previously charted, these EPYC CPUs will offer four different variants based on the reference usage type.

The first discriminant comes from the type of cores used, which can be either Zen 6 or Zen 6c. With the former, one can push up to 96 cores per socket (for 192 threads), while with the latter, the maximum now is 256 cores (512 threads). The type of integrated memory controller also changes: it can go up to 16 channels with MRDIMM modules or DDR5, while by opting for LPDDR5X memories one can achieve configurations of up to 24 channels.

AMD refers to Venice as a family of platforms, differentiated based on various elements to better adapt to different market segments and the various processing needs relating to artificial intelligence. The EPYC 9006 SP7 processors utilize SP7 sockets, with a maximum of 256 cores for Zen 6c variants and a bandwidth that can reach 1.6 TB/s. The integrated PCI Express 6 controller is 64 Gbps, while in Zen 6 architecture versions, the maximum reaches 96 cores with a clock frequency of up to 5 GHz. The first variant is the one that AMD uses in the Helios rack, intended to optimally manage the integrated GPUs in the system.

For the EPYC 9006 SP8 versions for SP8 sockets, variants are expected with a core count ranging from a minimum of 8 to a maximum of 128. The memory controller is 8-channel, with 128 PCI Express 6.0 lanes for connecting peripherals and different types of implementations based on specific system needs. The EPYC 9006X versions on SP7 sockets will have up to 96 Zen 6 cores with a 16-channel memory controller, capable of reaching a maximum bandwidth of 12.800 MT/s with MRDIMM memories and an L3 cache of 1152 MB. In very high levels, the clock frequency will peak at 5.1 GHz. The X suffix indicates the presence of 3D V-Cache, similar to previous generations of EPYC processors.

The last version is the EPYC 9006 LP, codenamed Verano, featuring a maximum of 72 cores paired with LPDDR5X memory to maximize efficiency. The maximum clock frequency will reach 5 GHz, while direct connectivity between CPU and GPU will be ensured by an Enhanced xGMI connection at 112 Gbps.

The Role of Connectivity

Given the complexity level of AI-related processing, with increasingly powerful CPUs and GPUs, the role of connectivity infrastructure is obviously becoming more relevant. Over the past few years, AMD has developed, thanks to some acquisitions, a comprehensive portfolio of proposals that meet the needs of the most complex data centers and fall within the AMD Helios rack concept.

These offerings belong to the AMD Pensando family, with different solutions based on specific usage. The third generation of AMD Pensando Salina DPU is designed for managing the Front-End. The second generation of AI NIC AMD Pensando Vulcano instead manages Scale-Out connections, with a significant increase in bandwidth reaching 2.4 Tbps per GPU. It's interesting to highlight how the proposals from the AMD Pensando family fall into the company's aim to provide a complete ecosystem for data centers while considering how CPUs and GPUs interact based on the service type required. AMD's offering is therefore a complete platform, whose ultimate realization is found in the AMD Helios design of a complete data center.

Physical AI: AMD and Robotics

Advancing AI 2026 is also an occasion for AMD to talk about the world of robotics, with differing types of robot usage in very diverse fields ranging from operating rooms to warehouses, agriculture, construction, and structural inspections. AMD's experience in these sectors is long-standing, having been present for over 20 years collaborating with market partners.

The evolution of AI agents will eventually lead, for certain applications, to having a physical AI agent taking the form of a humanoid, which will obviously require a high amount of processing power. This gives rise to the announcement of the Ryzen AI Embedded X100 solution, a Ryzen AI family processor specifically developed for the needs of robotic AI agents.

This processor is at the core of the AMD Kria AI system-on-module, a solution offered to partners that is a system mounted on a single 120x120 millimeter module that utilizes the open standard COM-HPC form factor. This module will in turn be the basis for the Kria AI Robotics Developer Platform, a complete platform that will be offered to development partners through which they can develop their own robotic solutions, significantly speeding up prototype development times.

Alongside the hardware solutions, AMD has announced its own AMD Robotics Software Suite, based on open standards, which also implements ROCm leveraging the CPU, GPU, and NPU architectures that AMD implements in the Ryzen AI Embedded X100 platforms. To incentivize the development of robotic solutions, AMD has also announced a specific initiative named AMD Robotics Partner Network, which gathers partner companies operating in this sector, with which to develop network products and solutions that can accelerate the development and market adoption of AI robotic solutions.

Will we soon see robotic AI agents in our homes and workplaces? It's hard to predict the timeline for all of this, but the fact that such solutions could become a concrete reality is just a matter of time, not willingness on the part of the industry as a whole.

AI at the Center of the World

The growth in the use of artificial intelligence is proceeding at a surprising rate: each passing month sees the number of AI processes being carried out in data centers increase at an exponential rate. The amount of FLOPS dedicated to training AI models has increased five times year on year since 2020, but as the years go by, the volume of processing is progressively shifting from training models to inference, meaning the use of agents by users. Currently, we are at a ratio of 60% for inference and 40% for training, a ratio that is destined to shift more toward the realm of AI agents.

This leads to a rapidly growing data center market, with an annual growth rate of 45% and a market value expected to increase sevenfold from 2025 to 2030. However, the world of artificial intelligence, in terms of processing capacity, is not confined just to data centers. The evolution of models is moving toward more compact sizes without loss of quality in the results provided: this is making AI models increasingly accessible for use at the edge, utilizing systems that are more compact and under direct user control. The hardware architectures that AMD offers to its partners and customers best cover both the training and inference needs typical of data centers and more complex models, as well as those of local clients that seek to operate independently from network connections to data centers.

It's evident that this will lead to a gradual spread of smaller, specific models, a dynamic that will proceed hand in hand with a shift in demand from training to AI agents, ultimately leading to physical AI agents that will assist us in our daily activities, both professional and personal. Will AI therefore accelerate the spread of robots in many fields where they can aid and improve the quality of work and personal life? This is one of the future bets that AMD, along with its partners, aims to take.