IBM Unveils World's First Chip Below One Nanometer: Nearly 100 Billion Transistors Achieved
IBM has presented today, June 25, 2026, the world's first chip below one nanometer: a transistor architecture of 0.7 nm, equivalent to a 7 angstrom node. This achievement arrives as the semiconductor industry struggles to keep pace with traditional miniaturization techniques, which are increasingly nearing their physical limits.
The new chip integrates nearly 100 billion transistors on a surface the size of a fingernail, nearly double the density achieved by IBM with the 2 nm chip introduced in 2021. This leap is made possible by a series of innovations in materials and structure, most notably the new three-dimensional nanostack architecture.
According to technical data released by the company, the chip can offer up to 50% more performance or up to 70% higher energy efficiency compared to IBM's 2 nm chips. This margin, on paper, benefits heavier workloads: generative artificial intelligence, cloud infrastructures, next-generation electronic devices.
"IBM's latest chip innovation marks a milestone in computing, capable of pushing technology beyond the nanometer era, towards the atomic scale," said Jay Gambetta, director of IBM Research and IBM Fellow. For Gambetta, nanostack is not just about miniaturizing transistors but redesigning the way chips are designed.
Nanostack, Vertically Stacked Transistors
Nanostack is the first three-dimensional nanosheet design in the industry, an evolution of the nanosheet technology that IBM itself had introduced as an industry benchmark. The underlying idea is to stack and offset transistors vertically, utilizing 3D sequential integration to increase density without further chasing horizontal miniaturization.
Each overlapping layer can utilize different materials, allowing for the optimization of performance and efficiency of each transistor independently of others. IBM has validated the architecture with ultra-thin dielectric bonding techniques, dual-channel engineering demonstrations, and the operation of CMOS inverters with switching performance consistent with expectations.
Research presented at VLSI 2026 also showed a 40% improvement in SRAM memory scaling, a significant statistic for chips expected to support the bandwidth needs of artificial intelligence applications. With this structure, logic technology dips below the 1 nm node for the first time, in the era of angstrom-level scaling.
IBM is advancing this work alongside partners at the research center in Albany, New York, where a high numerical aperture extreme ultraviolet (High NA EUV) lithography system developed by ASML will soon arrive. Among the partners involved in the development of processes and tools are Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions, which have already produced functioning devices with this technology.
On the production front, IBM estimates a path to manufacturing within the next five years. The company places this announcement within its history of semiconductor development, from the first chips of the 1960s to the world's first 2 nm chip, and aligns it with another recent project: Anderon, the independent company with which IBM aims to create the world's first foundry dedicated solely to the production of quantum wafers.