AI Forces Acceleration of Technological Development: TSMC to Advance CoPoS Debut

The growing demand for AI accelerators is pushing the semiconductor industry to seek new solutions in the field of advanced packaging. According to the latest information from the supply chain reported by analyst Ming-Chi Kuo, TSMC plans to start mass production of CoPoS technology in the second half of 2028, moving up the timelines that were previously suggested.

The new solution, referred to by the acronym CoPoS (chip-on-panel-on-substrate), aims to overcome some limitations of the current CoWoS (chip-on-wafer-on-substrate) technology, which is widely used for assembling the most advanced AI chips on the market.

Key takeaways on TSMC's next-generation advanced packaging, CoPoS (publicly available technical details omitted):

1. CoPoS is currently expected to enter mass production in 2H28. It is designed to improve the economics of ultra-large packages above the 9.5x reticle-size class, — Ming-Chi Kuo (@mingchikuo) June 11, 2026

The industry's focus remains particularly high as the demand for hardware dedicated to artificial intelligence continues to grow, and TSMC plays a central role in the production of the most sophisticated semiconductors. In recent months, various rumors have highlighted interest in alternative technologies such as Intel EMIB-T, while NVIDIA is reportedly considering different approaches for future accelerators in the Feynman family.

According to Kuo, NVIDIA could become one of the first customers to adopt CoPoS, leveraging the advantages offered by the new packaging architecture. The main benefit concerns the ability to create packages of significantly larger sizes compared to current ones, with surfaces that can exceed over nine times those of a standard mask used in lithographic processes.

The current CoWoS technology uses a silicon interposer that serves as a high-performance link between GPUs, memory, and other components integrated into the same package. The realization of this element depends on lithographic processes and the sizes of the corresponding masks, a factor that introduces physical constraints on the overall size of the package.

With CoPoS, on the other hand, TSMC will eliminate the traditional interposer in favor of a structure based on larger panels, which serve as an intermediary element between the chips and the final organic substrate. This choice allows for a significant increase in the area available for integrating components.

From a construction standpoint, information shared by the analyst indicates that the technology will initially use temporary glass supports during the assembly phases. Subsequently, components will be transferred to a glass substrate encapsulated between layers of Ajinomoto Buildup Film (ABF). In this configuration, the use of a glass interposer is not envisioned: the chips are connected directly to the ABF layer of the substrate.

Looking to the future, the increase in package size will allow for integrating more high-performance components within the same solution, a requirement that is becoming increasingly relevant to sustain the growth of computational power demanded by the most advanced artificial intelligence models.