Interconnections at 1 Micrometer: CEA-Leti Pushes the Limits of 3D Integration

CEA-Leti has announced an important milestone in the field of three-dimensional integration of semiconductors, presenting a functioning test vehicle at ECTC 2026 based on die-to-wafer (D2W) hybrid bonding technology with a reduced interconnection pitch of up to 1 micrometer.

This advancement pushes towards increasingly dense architectures and could help address some of the key limitations that the semiconductor industry faces in continuing the path of miniaturization traditionally associated with Moore's Law.

Interest in 3D stacking technologies has grown rapidly in recent years, especially in areas such as high-performance computing (HPC), artificial intelligence, and advanced vision systems. In these sectors, the density of interconnections between different dies is a determining factor for increasing available bandwidth while simultaneously reducing energy consumption. The D2W approach allows for vertical stacking of multiple layers of devices, significantly shortening the distance data must travel compared to traditional horizontal connections.

According to the French research center, the electrical characterization of the tested structures confirmed the correct functioning of configurations with up to 100,000 connections. Tests showed results in line with expectations for pitches between 5 and 2 micrometers, while the transition to the 1 micrometer threshold highlighted that the alignment precision of current bonding tools still represents the main technological limit.

Achieving such a reduced pitch required particularly complex work in terms of alignment and surface planarization. A central role was played by the Inter-Die Gap Filling (IDGF) process, used to fill the spaces between dies during wafer reconstruction. This step required optimization to ensure sufficiently uniform surfaces compatible with subsequent vertical connections.

CEA-Leti believes that the arrival of a new generation of tools capable of ensuring alignment precision of 0.5 micrometers (3σ) could significantly improve production yields even for 1 micrometer interconnections. The result achieved is also described by researchers as the first known example of copper-copper die-to-wafer bonding with a pitch of 1 micrometer.

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However, this demonstration is merely an intermediate step in a broader roadmap. Upcoming developments foresee the integration of D2W bonding with other vertical interconnection technologies, including high-density Through-Silicon Vias (HD TSV) and Through-Oxide Vias (TOV). The goal is to create increasingly complex multi-die architectures, in which different chips and functions can be combined within the same package while maintaining extremely dense vertical connections.

The research center is already looking at the next generation of technology, with the declared aim of developing a new test vehicle capable of achieving a pitch of just 0.5 micrometers. An even higher density could prove particularly interesting for future generations of accelerators dedicated to artificial intelligence and for new-design CMOS sensors.

According to the researchers involved in the project, the combination of die-to-wafer and wafer-to-wafer technologies could also help find a balance between performance and production costs, an increasingly important aspect as the complexity of chips continues to rise.