Forget Moore's Law, HUAWEI Targets the Tau Scaling Law for Semiconductors: What Is It About
In occasion of the IEEE International Symposium on Circuits and Systems 2026, HUAWEI presented a new vision for the evolution of the semiconductor industry, proposing an alternative approach to the traditional Moore's Law. During the keynote titled "New Semiconductor Path in Practice", He Tingbo introduced the so-called Tau Scaling Law, a "law" aimed at replacing the concept of geometric scaling with a strategy based on reducing time constants in electronic circuits.
According to the company, the industry is facing a particularly delicate moment. After over fifty years of progress driven by transistor miniaturization, the physical limits of advanced manufacturing processes and the increasing difficulty in further reducing costs per transistor are slowing the traditional evolution of chips. In this context, HUAWEI believes it is necessary to identify a new path capable of sustaining the growth of computational demand, especially in the AI and mobile sectors.
The Tau Scaling Law is based on the idea of optimizing the signal propagation time within electronic systems, intervening simultaneously at multiple levels of design. The stated goal is to progressively compress the time constant τ to increase performance, energy efficiency, and transistor density without relying exclusively on the advancement of lithographic processes.
τ = RC
At the device level, the strategy involves reducing resistance and parasitic capacitance in transistors and interconnections, elements that directly influence switching times and signal propagation.
On the circuit front, HUAWEI presented a new architecture called LogicFolding. According to the company, this technology would allow overcoming some physical limits of traditional circuit arrangements, shortening critical signal paths and reducing the resistive and capacitive load associated with interconnections. The expected effect is an increase in transistor density accompanied by an improvement in overall performance.
At the chip level, the company speaks of coordinated design involving software, architecture, and silicon. The goal is to achieve more targeted control of instruction and data flows based on workload, increasing parallelism and reducing end-to-end execution times.
The system infrastructure is also part of the strategy outlined by HUAWEI. The company mentioned UnifiedBus, a technology designed to redefine interconnection protocols in high-performance computing systems. The solution is expected to allow unified addressable memory and native memory semantics within SuperPoD configurations, aiming to reduce latency in communications between nodes.
During the presentation, it was also highlighted how the Tau Scaling Law has already been applied to numerous commercial projects. HUAWEI claims to have designed and produced 381 chips based on these principles in six years, targeting various sectors and markets.
Particular attention was given to the next generation of Kirin SoCs expected for autumn 2026. According to statements made, these chips will be the first to adopt the LogicFolding architecture in commercial products, with expected performance benefits.
Finally, HUAWEI indicated a particularly ambitious long-term goal: by 2031, high-end chips developed following the Tau Scaling Law should achieve a transistor density equivalent to manufacturing processes at 14 angstroms, or about 1.4 nanometers.
During the presentation, He Tingbo emphasized that the future of the semiconductor industry requires collaboration among companies, researchers, and technology partners, stressing that no single actor would be able to tackle the challenges posed by the next evolutionary phase of the sector.