Samsung and SK hynix Compete for the Future of DRAM: Different Solutions, Similar Goals

Samsung and SK hynix are reportedly engaged in a new technological competition to define the architecture of future DRAM memory, deemed essential to support the growing demand for infrastructure dedicated to artificial intelligence.

According to industry sources, the two South Korean giants are pursuing different paths to overcome the production limitations of current memories and gain a strategic advantage in the market for chips destined for AI data centers. The expansion of artificial intelligence systems and large computing centers has indeed increased pressure on the advanced memory supply chain, creating strong demand for technologies like HBM and DRAM, which share similar raw materials and production processes.

Samsung is considering the use of GAAFET technology for the development of the next generations of DRAM. This solution, already employed in processors, involves the transistor's gate completely wrapping around the conduction channel, improving electrical flow control and increasing component efficiency. However, in the case of DRAM memories, the situation is more complex because each cell must also include a capacitor responsible for storing the data. With the miniaturization of production processes, maintaining adequate sizes for these components becomes increasingly challenging.

Samsung and SK Hynix: New Technologies Under Development
To tackle this problem, Samsung is reportedly thinking of applying an architecture inspired by NAND memories. The idea would be to shift part of the circuitry dedicated to reading and writing operations beneath the memory array, thus optimizing the available space within the chip.
"Samsung Electronics has found a solution by arranging the capacitors horizontally - which tend to tip over when positioned vertically - and stacking them in layers, simultaneously adopting the Peri-on-Cell (POC) method. This approach involves placing the circuit (Peri) at the bottom and the cell (Cell) on top. It is an adaptation of the Cell-on-Peri (COP) method, utilized in NAND flash memories, to DRAM," reports the Etnews website.

Meanwhile, SK hynix is developing an alternative solution based on the approach called 4F². In this model, the transistors are arranged vertically and surrounded by gate material, in a configuration that echoes some principles of GAAFET technology. Again, the components responsible for managing the data coming from the capacitors would be placed beneath the main structure of the transistor, aiming to increase density and production efficiency.

The memory sector is progressively orienting toward three-dimensional DRAM structures, deemed necessary to continue miniaturization beyond the limits of traditional two-dimensional architectures. More advanced technologies indeed allow for increased transistor density, but they also raise the risk of interference between excessively close components. According to reports, Samsung and SK hynix are seeking to have their approach recognized as the future industrial standard for next-generation DRAM.