Samsung Foundry Updates Roadmap: SF1.4+ Process Expected by 2030

Samsung outlined its future chip production plans during the SAFE Forum 2026 (Samsung Advanced Foundry Ecosystem), the traveling event dedicated to the semiconductor division of the Korean group. Some of the details had already been leaked in previous months.

Among the main innovations is SF1.4+, a second 1.4-nanometer process that, according to the company's forecasts, is expected to debut around 2030. This is not the first time Samsung has revised its roadmap downwards: the 1.4 nm process was originally scheduled for 2027, then pushed back to 2029. The arrival of an optimized version (SF1.4+) just one year later, with improvements in performance, power consumption, and density (the three parameters summarized in the acronym PPA - Power, Performance, Area), fits within the established practices of the industry, making the 2030 deadline plausible.

The forum also confirmed the SF2X process, intended for the HPC (High Performance Computing) segment and designed to complete the 2-nanometer process portfolio, which already includes SF2, SF2P, and SF2P+. However, the timelines have also slipped compared to initial forecasts: SF2P+ is now expected in 2027-2028, and only from it will SF2X be developed, which will still maintain full compatibility with SF2P and SF2P+. Originally, SF2P was scheduled for 2026, with SF2X partially parallel to it.

The situation of SF2Z, the first Samsung process featuring Backside Power Delivery (BPD), announced back in 2024, is more critical. Currently, there is no trace of this technology in official communications, and Samsung has yet to release an updated roadmap clarifying its fate.

It is worth noting what these designations actually indicate: SF stands for Samsung Foundry, the following number refers to the manufacturing node expressed in "nanometers," while the additional letters specify the variant: P for Performance, A for Automotive, X for the more advanced version, Z for Backside Power Delivery. However, for some time, these names have lost any direct link to a real physical measurement in nanometers, transforming into marketing labels used to position products against competitors like TSMC and Intel, who in turn adopt their own conventions that are not directly comparable.

The topic resurfaced recently after IBM's intervention on the matter: Intel's CTO, Pushkar Ranade, reiterated on X that these designations do not reflect the actual sizes of transistors. Elon Musk also participated in the discussion, suggesting that production processes should be named based on the number of atoms that make up the minimum feature size. "In my opinion, that would be the most accurate solution."