Forget transistors, the real limitation of chips lies in the interconnections. And, perhaps, we have the solution
With the global semiconductor market heading towards the threshold of one trillion dollars in annual revenue, the race for increasingly faster and more efficient chips is encountering a less visible obstacle than transistors: the tiny copper interconnections that link the internal circuits of processors.
The problem is not so much the copper itself, but the materials that coat it. In modern chips, each copper wire actually requires two protective layers: a barrier that prevents copper atoms from migrating into surrounding materials, causing short circuits, and a liner that promotes the adhesion of copper to the substrate and the formation of uniform connections.
Current industrial solutions, primarily based on tantalum materials, require thicknesses of several nanometers. In future generations of chips, however, these coatings risk occupying up to half of the wire's section, significantly increasing electrical resistance and limiting performance and energy efficiency.
To address the problem, researchers from the National University of Singapore and Applied Materials have developed a process that enables the growth of crystalline films of tungsten disulfide (WS₂) just 0.7 nanometers thick, which is only a few atoms, on 200 mm industrial wafers.
The study, published in Nature Electronics, shows that a single atomic layer of WS₂ can simultaneously serve as both liner and barrier, paving the way for thinner interconnections without compromising speed and reliability. Tests have highlighted that the WS₂ coating helps copper to form a continuous and uniform film instead of aggregating into separate islands, a problematic phenomenon when thicknesses become extremely thin.
According to the researchers, electrical resistance has decreased by over a million times compared to uncoated surfaces. Moreover, the single layer of WS₂ has achieved performance about five times better than the traditional tantalum stack while being nearly ten times thinner.
The advantage becomes particularly evident in a hypothetical interconnection width of 20 nanometers: the conventional coating would occupy about 40% of the wire's diameter, while WS₂ only 7%, leaving much more space for copper to carry current.
One of the most interesting discoveries pertains to the material's behavior as a barrier. Computational models developed by the Department of Chemistry at NUS have shown that WS₂ grows with a polycrystalline structure composed of many small grains oriented randomly. Instead of representing a defect, this arrangement creates a sort of structural maze: the grain boundaries do not align across the layers, making the passage of copper atoms through the coating much more difficult. "The polycrystalline nature of these films, which might seem like a limitation compared to a perfect crystal, actually proves to be an advantage," explained Professor Richard Wong from NUS.
In durability tests, WS₂ prevented copper from reacting with the underlying silicon even after prolonged heat exposure. Under electrical stress, the new coating also extended the anticipated operational life of the interconnections by over ten times compared to unprotected devices.
A relevant aspect of the work is the attention to industrial compatibility. The growth process, based on thermal atomic layer deposition (ALD) without plasma, operates at 350 °C, a temperature low enough not to damage the layers already present on the chip. The team claims that the technique simultaneously meets four key requirements for integration into production lines: low processing temperature, uniform coverage of the entire wafer, atomic-level thickness control, and conformal coating of deep and narrow trenches with over 95% coverage.
According to the researchers, the layers obtained are thinner than any target anticipated by international roadmaps for barriers and liners until 2037, suggesting potential use not only in the next generation of chips but also in subsequent ones. Future activities will focus on a detailed study of the two-dimensional interface and the potential control of grain orientation to further enhance performance and long-term reliability.