Intel 18A-P is Already in Risk Production. Here are All the Improvements in the Production Process

At the VLSI Symposium 2026, Intel Foundry announced that Intel 18A-P - the first performance optimization in the Intel 18A family - has reached the risk production phase, adhering to the roadmap outlined by Intel for 2025. Risk production represents an intermediate phase between process development and high-volume production: customers can start creating the first commercial chips while Intel continues to optimize yield and production parameters.

To understand the significance of Intel 18A-P, it is essential to briefly frame the process it is based on. Intel 18A is the process node with which Intel Foundry introduced two fundamental technologies into production: gate-all-around (GAA) transistors and backside power delivery (BSPD), marketed as PowerVia. The combination of these two technologies marks a generational leap from FinFET architectures, and Intel is the first company to bring them into high-volume production simultaneously.

According to shared data, the defect density (D0) of Intel 18A has continued to decline more rapidly than the company's internal projections starting from Q3 2024, with a descending curve that has surpassed internal forecasts. The process is already powering client products like Panther Lake, with those intended for data centers expected to follow later. Production takes place in two U.S. facilities.

Intel 18A-P: What It Is and What Changes

Intel 18A-P is not a radically different process from its predecessor, but rather a targeted optimization that maintains full compatibility with Intel 18A. This means that existing designs can be reused without starting from scratch, an advantage not to be overlooked for customers who have already invested in IP and design flows for 18A.

Intel claims that 18A-P offers a tangible improvement in the performance-to-efficiency ratio compared to 18A. Using a fully routed standard Arm core as a reference, the company indicates:

+9% frequency at iso-power
-18% power at iso-performance
-20/40% thermal resistance
-10/30% Via resistance in the critical layers for performance

These numbers position 18A-P competitively in the landscape of advanced processes, with an improved PPA (Power, Performance, Area) profile that does not require a complete design migration.

Power Boost and More

Among the most significant innovations in Intel 18A-P is Power Boost, the new option with low-resistance double-contact transistors that allows the transistor to deliver more current and reach higher frequencies without significantly increasing power consumption. The distinguishing feature is the presence of both a front-side contact and a direct backside contact, the latter enabled by the PowerVia technology already present in 18A.

Another significant technical feature concerns the offering of voltage thresholds (Vt). Intel 18A-P brings the available logical VT pairs to five, adding an intermediate ULVTLL (Ultra Low Voltage Threshold Low Leakage) pair between ULVT and LVT. This additional pair allows designers to optimize the speed/power ratio with greater granularity than its predecessor, with the possibility of adding further intermediate pairs as design needs require.

Thermal Improvements

A often underestimated theme in advanced processes is thermal management. With increasingly dense transistors and multi-layer architectures, heat becomes a design constraint as much as power and frequency. Intel 18A-P addresses this issue on multiple fronts: on one hand through material optimizations that improve thermal conductivity, and on the other through design innovations supported by advanced EDA flows.

The stated result is a thermal resistance reduction between 20% and 40%. Lower thermal resistance means that the heat generated by the transistors is dissipated more rapidly. This allows for sustained high frequencies for a longer duration and reduces the risk of the chip needing to automatically throttle performance to contain temperatures.

BSPD + GAA: Intel Quantifies the Benefits of the Pairing

Intel Foundry has also quantified the benefits arising from the combination of Backside Power Delivery (BSPD) and GAA transistors, the two technologies introduced with 18A. Eric Karl, Vice President and Fellow of Intel Foundry, stated that he has reduced the phenomenon of dynamic voltage droop, that is, the temporary voltage drops that occur when the chip rapidly transitions from a light to a heavy load, by an order of magnitude, thanks to the elimination of parasitic resistance introduced by front distribution networks. This allows for a frequency increase of up to 6% or a dynamic power reduction exceeding 15% compared to a comparable front interconnection technology. Manju Shamanna from Intel Foundry's Silicon and Platform Engineering group presented results related to cores made with a "gate-all-around" process and backside power delivery. Her research demonstrates greater frequency scalability at lower voltages, including an improvement of around 30% at low voltage (~0.5 V), while reducing voltage drop and achieving more efficient operation.

The Roadmap: Beyond GAA

Aside from updates on 18A-P, Intel used the VLSI Symposium to showcase some of the technologies that could characterize manufacturing processes over the next decade:

Complementary FET (CFET): considered the next major evolution of transistor architecture, CFET technology vertically stacks NMOS and PMOS within the same planar footprint, allowing for the continued scaling of logic density beyond the physical limits of gate-all-around. Intel demonstrated a monolithic CFET inverter with PMOS on NMOS at a gate pitch of 45nm, one of the most advanced publicly shared results on this architecture.
GaN + Silicon Logic: Intel demonstrated monolithic integration on 300mm wafers of power devices in gallium nitride with silicon logic, integrating a digital control block of about 1,000 gates. This combination allows the high-voltage switching features of GaN to be combined on a single die with CMOS logic density, reducing system complexity and potentially lowering packaging costs.
Subtractive Ruthenium (sRu) with Airgap: to tackle the challenge of interconnections as distances shrink, Intel demonstrated a subtractive ruthenium interconnection with airgap integration, achieving a reduction in parasitic capacitance of about 35% and measurable frequency gains compared to copper. This approach outlines a feasible pathway beyond copper for future processes.

In Summary

With 18A-P, Intel does not introduce a revolution comparable to the transition from FinFET to RibbonFET and PowerVia, but proposes an incremental evolution of 18A aimed at improving performance, efficiency, and thermal management while maintaining compatibility with existing designs. For Intel Foundry, this is also an important commercial step, as it demonstrates the desire to build a competitive and rapidly iterable family of processes, following a model already adopted by other major semiconductor manufacturers.