Goodbye Silicon? Imec, ASML, and TSMC Showcase 2D Transistors Compatible with Advanced Processes
Imec, ASML, and TSMC have announced a significant advancement in the development of transistors based on two-dimensional (2D) materials, presenting a new integration methodology on 300 mm wafers at the IEEE/JSAP Symposium on VLSI Technology and Circuits 2026, aimed at bridging the gap between academic research and industrial production.
The collaboration between the Belgian research center, the lithography solutions provider ASML, and the Taiwanese foundry TSMC has enabled, for the first time, the realization of nFET and pFET transistors based on materials from the family of transition metal dichalcogenides (TMD) with a contacted poly pitch (CPP) of 50 nanometers, which is the minimum center-to-center distance between two adjacent transistors on a chip.
The devices use MoS2 (molybdenum disulfide) as the channel material for nFETs and WS2 (tungsten disulfide) or WSe2 (tungsten diselenide) for pFETs. According to the researchers, the results obtained represent a crucial step toward the industrial adoption of 2D transistors, candidates for extending the miniaturization roadmap beyond the limits of traditional silicon.
TMD materials have attracted the interest of the semiconductor industry for years because, due to their atomic thickness, they allow excellent electrostatic control of the channel even with extremely short lengths, while still maintaining a sufficiently high carrier mobility. Until now, however, the transition from research to production has been hindered by the difficulty of integrating 2D transistors on 300 mm wafers with sizes compatible with industrial needs without compromising the performance demonstrated in research laboratories.
The new solution proposed by imec, ASML, and TSMC specifically addresses this problem. In addition to the record CPP of 50 nm, the process has enabled achieving very low leakage currents (Ioff) with gate voltages of zero for both polarities of the transistors and performance of WSe2-based pFETs close to those of the best experimental devices made in laboratories.
Another relevant element concerns the robustness of the manufacturing process. The researchers report a functionality rate of 94% for the transistors produced. The integration approach, described as "CMOS-like", allows the co-existence of nFETs and pFETs on the same 300 mm silicon surface, demonstrating stability compatible with future production applications.
To achieve these results, the contribution of EUV lithography has been crucial. Gouri Sankar Kar, Vice President R&D Compute and Memory Device Technologies at imec, explained that 2D material-based transistors are usually optimized for very short channels but require large contact areas to contain electrical resistance, thus limiting the possibility of further reducing device sizes. Thanks to a single-exposure EUV process developed together with ASML, it was possible to achieve the 50 nm CPP without penalizing electrical performance.
From an architectural standpoint, the work also introduces an innovative production flow defined as "reverse TFT". Unlike conventional 2D transistors, the new devices employ lower contacts and an overlapping deposited gate. The active material is transferred over previously fabricated trenches filled with tungsten, which serve as electrical contacts. This configuration contributes to achieving the ideal behavior observed in tests, with both types of transistors turning off correctly when the gate voltage is zero.
Although the technology is still in research and development, this demonstration represents one of the most significant advancements made so far toward the industrialization of 2D material-based transistors, one of the possible paths the semiconductor industry is exploring to continue the miniaturization journey beyond the capabilities of conventional silicon.