RISC-V Looks to Datacenters: NextSilicon is Preparing the Arbel CPU with up to 128 Cores

NextSilicon has announced the roadmap that will lead its RISC-V core Arbel to become a processor intended for datacenters, with versions of 64 and 128 cores expected in the first quarter of 2028. The Israeli company, known for the Maverick-2 accelerator, believes — like the rest of the industry — that the evolution of AI-based workloads is bringing attention back to CPU performance, especially in areas where serial logic remains a determining factor.

Arbel does not originate as a standalone processor but as an internal component of the Maverick-2 accelerator. In this configuration, the core handles serial operations, system management, and data movement that cannot be parallelized by the dataflow architecture used by the accelerator. The use in production environments has allowed NextSilicon to validate its performance with real workloads even before the realization of a dedicated chip.

To verify the architecture outside the accelerator context, the company later created a test chip manufactured with TSMC's 5-nanometer process. According to data shared by NextSilicon, the project integrates a pipeline capable of issuing up to 10 instructions per cycle, a reorder buffer with 480 entries, and a retirement capability that can reach 16 scalar instructions per cycle. There are also 128-bit vector units dedicated to parallel processing and AI inference workloads, while the operational frequency of the test chip reaches 2.5 GHz. Support for standard Linux distributions completes a platform designed for server and HPC applications.

Evaluations conducted by customers and partners, including datacenter operators, AI infrastructure architects, and HPC program managers, have reportedly confirmed the performance characteristics of the project and contributed to defining the requirements for the commercial version. This led to the decision to develop a full processor based on Arbel.

The future CPU will expand the architecture to 64 or 128 high-performance cores and adopt a more advanced manufacturing process compared to that used for the test chip. The stated goal is to reach frequencies of around 3.4 GHz while simultaneously improving density and power consumption, which are crucial aspects in modern datacenter infrastructures. However, some key elements of the architecture will remain unchanged, including the TAGE branch predictor, designed to compete with the most advanced implementations in the x86 and Arm markets.

NextSilicon anticipates two main usage scenarios. On one hand, Arbel will serve as a standalone server processor, providing companies with a RISC-V alternative to reduce reliance on the roadmaps and licensing models typical of proprietary architectures. On the other hand, the CPU will function as a host processor for the Maverick platform, coordinating accelerators and data flows in heterogeneous configurations dedicated to AI and HPC. The processor will comply with RVA23 specifications and be compatible with major Linux distributions. The company has already initiated contacts with potential customers interested in evaluating the adoption of the future RISC-V solution.